(1) Field of the Invention
The present invention relates generally to the structure and manufacturing process of a semiconductor device isolation structure for electronic circuit devices and more particularly to a shallow trench isolation (STI) structure with improved field oxide coverage in the top corners near active device areas.
(2) Description of Prior Art
Various field oxide (FOX) isolations are used to electrically isolate semiconductor devices such as field effect transistors (FETs) formed on semiconductor substrates to form integrated circuits. This FOX is formed on single crystalline silicon (Si) for Large Scale Integration (LSI) and Ultra Large Scale Integration (ULSI) circuit applications. One common method of forming the field oxide is by the local oxidation of silicon (LOCOS) method. This method uses a patterned silicon nitride (Si3N4 or SiN) together with a thin layer of pad oxide (SiO2) for stress relief and the silicon substrate is selectively oxidized to form the semiconductor isolation. This method requires long oxidation times (excessive thermal budgets), and the lateral oxidation under the barrier mask limits the minimum spacing between adjacent active device areas and therefore can become a limiting factor in increasing device packaging density.
A more advanced isolation scheme is to etch shallow trenches in the silicon substrate which are then filled with a chemical vapor deposited (CVD) silicon oxide (SiO2), or some other dielectric. These trenches are typically on the order of 0.25 to 0.35 microns (um) in depth and 0.15 to 0.5 um in width. After the shallow trench isolation (STI) structure is filled with the dielectric, an etchback or chemical mechanical planarization (CMP) step is typically performed. Processing continues with either a capping process or with FET device processing.
However, a typical problem with the conventional prior art STI methods is the reduction or lack of insulator coverage on and around the upper corners of the trench structure. FIG. 1 shows a prior art STI structure. As indicated in FIG. 1A, the structure was formed by the process which started with the substrate 10 upon which a stress relief pad oxide (SiO2) layer 12 has been thermally grown, and then a layer of silicon nitride (SiN) 14, has been deposited using CVD process well understood in the industry. Conventional photolithographic techniques have been used to pattern the SiN 14 and pad oxide 12 to enable a trench 18 to be etched in the substrate 10. The etching process is typically a dry anisotropic process. After etching, the photoresist used for patterning is removed and a thermal oxide layer 19 is grown within the trench as a liner to maintain trench geometry and prevent structure damage during further processing. A low pressure CVD (LPCVD), a sub-atmosphere CVD (SACVD), or high density plasma silicon oxide (SiO2) 30 is then deposited to fill the trench 18 as shown in FIG. 11B. The trench fill CVD silicon oxide is etched back or chemical mechanical polished (CMP) back to the silicon nitride layer 14. This planarization step is typically not very selective and is difficult to control within the required processing tolerances. The SiN 14 layer is next selectively removed using a hot phosphoric acid (H3Po4) etch typically in the 150 to 180 degrees centigrade (xc2x0C.) range, and the pad oxide is removed using dilute hydrofluoric (HF) acid. Frequently, due to etch rates and edge coverage thickness and other process parameters, the field oxide coverage at the upper edge of the STI corners approaching the active device areas can have thin coverage or void 4 as indicated in FIG 1C. This void can cause device operating problems such as current crowding and edge wrap around effects, result in poor gate oxide insulating properties and pose potential reliability exposures.
U.S. Pat. No. 6,001,706 issued to Tan et al., shows a STI process with a doped polysilicon hard mask and an oxide liner.
U.S. Pat. No. 5,960,298 issued to Kim shows an oxide STI trench liner
U.S. Pat. No. 5,940,717 issued to Renegarajan et al. teaches a SiN trench liner.
U.S. Pat. No. 5,989,978 issued to Peidoous teaches a STI process with a liner and barrier layers.
Accordingly, it is the primary objective of the invention to provide an effective and manufacturable method and structure for an improved shallow trench isolation (STI) element on silicon substrates having improved quality and coverage of the insulating oxide on the structure corners near the active device areas.
It is a further objective of the invention to improve device isolation and operational characteristics by increasing the oxide coverage at the STI corners near the active device areas.
In addition, it is an objective of this invention to provide a polysilicon layer over the device areas that is laterally oxidized to provide a portion of the field oxide extending over the device area thereby minimizing or eliminating the corner oxide voids and consequent detrimental wrap-around effect.
It is yet another object of the invention to provide a method for forming an STI isolation structure with reduced mechanical stress, and improved gate oxide integrity,
The above objectives are achieved in accordance with the methods of the invention that describes a structure and a process for manufacturing semiconductor devices with improved STI corner coverage in the active device regions. Beginning with a semiconductor substrate of single crystal silicon, either N or P doped, a first thermal oxide layer is grown thereon to provide a stress release pad oxide. A silicon nitride (SiN) is deposited on the pad oxide layer by LPCVD to be used as a hard mask to pattern the STI element in conjunction with conventional photolithographic methods. An anisotropic plasma etch is used to etch the SiN layer, the pad oxide layer, and to partially etch into the silicon substrate to form trenches where the isolation structures are required.
Now, by the method of the invention, a conformal silicon layer is deposited onto the open trench and on the SiN pad and pad oxide layers where exposed. The deposited silicon can be either amorphous, epitaxial or polysilicon. Typically after depositing the silicon layer an implant is done using silicon as the specie at an energy of between 30 and 50 KeV. The silicon layer is then annealed to form epitaxial silicon where the layer was in contact with the silicon substrate and polysilicon elsewhere. Next, a thermal oxidation is carried out to form a liner oxide layer over the conformal silicon layer. There follows a conformal CVD silicon oxide deposition to fill the trenches and form a trench or gap fill oxide. The CVD oxide is preferably deposited using a low pressure CVD (LPCVD), a sub-atmosphere CVD (SACVD), or a high-density plasma CVD (HDP-CVD). A gap oxide densification step can optionally follow.
The gap fill oxide is then polished back to the nitride layer, and the SiN is selectively removed using a hot phosphoric acid (H3PO4) etch. This leaves a layer of polysilicon (poly) adhering to the vertical sides of the gap fill oxide slightly over the active device area where the SiN layer was removed. The pad oxide can now be removed using a dilute hydrofluoric (HF) acid, after which a final thermal oxidation is done converting the vertical poly layer into a thermal oxide. It should be noted that the oxide from this poly layer oxidizes 2 to 3 times faster than the oxide formed from the silicon substrate, assuring that the oxide extends over the edge of the device areas. Since this oxide layer is not suitable for the gate oxide layer, it is removed, typically with dilute HF. It is important to note that since the thermal oxide formed from the poly layer etches at a slower rate than the other oxide, an appropriate portion of the field oxide over the edge of the device area remains after etching to prevent unwanted voids or detrimental wrap around corned effects.
An alternative process would be to perform the last STI oxidation step with the pad oxide in place, then remove the pad oxide at the same time as the removal of the final STI oxide from the active device area. Again, because of the slower etch rate of the thermal oxide crated from the poly layer, there will still remain a portion of the field oxide over the active device areas to provide the structure quality and performance enhancements mentioned above.